This invention relates to a semiconductor apparatus manufacturing method, which features an improved method of isolating elements.
In recent times, the isolating of various elements such as a transistor, diode, and resistor, all deposited on the same substrate of a semiconductor integrating circuit, has tended to be accomplished by use of the trench isolation process. Using this process, a groove is formed in a semiconductor substrate, a polycrystalline silicon layer is embedded in the groove, and an insulation layer is interposed therebetween, thereby to isolate the respective elements. This process has the merit of reducing the size of isolation region and, consequently, the parasitic capacitance.
FIGS. 1A-1D show the sequential steps of a semiconductor apparatus-manufacturing method using the conventional trench isolation process.
First, the surface of silicon substrate 31 is oxidized, thereby forming oxide layer 32. Then, silicon nitride layer 33 is formed on oxide layer 32, followed by silicon oxide layer 34 being formed on silicon nitride layer 33, by way of chemical vapor deposition (CVD). Silicon oxide layer 34 acts as a mask during the etching of substrate 31. Photoresist layer 35 is coated on silicon oxide layer 34. Light exposure and development are applied on photoresist layer 35, thereby performing patterning (FIG. 1A).
Subsequently, silicon oxide layer 34, silicon nitride layer 33, and oxide layer 32 are selectively etched in succession, with photoresist layer 35 serving as a mask. Thereafter, photoresist layer 35 is removed, and silicon substrate 31 is selectively etched, thereby forming groove 36 by means of the anisotropic etching process, involving use of the reactive ion etching (RIE) process and of silicon oxide layer 34 as an etching mask. Thereafter, silicon oxide layer 34 is removed. After silicon oxide layer 37 is formed on the inner periphery of groove 36, polycrystalline silicon layer 38 is grown to a thickness equivalent to twice the width of groove 36 (FIG. 1B).
Then, polycrystalline silicon layer 38 is etched until the surface of silicon nitride 33 is exposed. As a result, polycrystalline silicon layer 38 is retained only in the interior of groove 36 (FIG. 1C).
The surface of layer 38 retained inside of groove 16 is oxidized, by using silicon nitride layer 33 as an acidproof mask thereby forming thick field oxide layer 39 (FIG. 1D). Later, elements are formed on portions of the semiconductor apparatus other than groove 36.
However, the aforementioned trench isolating process is accompanied with the following drawbacks:
.circle.1 Thick polycrystalline silicon layer 38 has to be applied to fill up groove 36. A long time has to be consumed in the growth and etching of thick polycrystalline layer 38.
.circle.2 Difficulties arise in the etching of thick polycrystalline layer 38; for example, stepped portions tend to be formed in groove 36.
Referring to the drawback described in .circle.2 , if the width of groove 36 is 1.5 microns, polycrystalline silicon layer 38 must have a thickness of around 3 microns. Consequently, a stepped portion higher than 1 micron will be formed due to variations in the thickness of polycrystalline silicon layer 38 and in the extent of etching.
With the aim of resolving the above-mentioned difficulties, Japanese patent disclosure No. 57-60851 sets forth the following process:
This process involves causing only the upper portion of the groove to be inclined slightly, so as to prevent the stepped portion from rising steeply. The process is, however, defective in that the element-isolating region is inevitably made wider than groove 36, and moreover, a certain limitation is imposed on the contraction of the element-isolating region.
In addition, an oxide layer grown in a field region other than the element section has to be grown quite thick, in order to reduce the line capacity or to increase the reliability of the integrated circuit. A formation of a field oxide layer by means of oxidizing the silicon substrate tends, as has already been explained, to give rise to crystalline defects occuring in the neighborhood of groove 36. In the process of FIG. 1D, when thick silicon oxide layer 39 is formed by oxidizing the surface of polycrystalline layer 38, that portion of substrate 31 which lies near groove 36 is adversely oxidized at the same time, thereby increasing the incidence of crystalline defects in substrate 31.